Module `SIL.Domain`

abstract domain whose state we propagate

include AbstractDomain.NoJoin

include IStdlib.PrettyPrintable.PrintableType

type t

val pp : IStdlib.PrettyPrintable.F.formatter -> t -> unit

val leq : lhs:t -> rhs:t -> bool: the implication relation: lhs <= rhs means lhs |- rhs

val join : t -> t -> t
val widen : prev:t -> next:t -> num_iters:int -> t